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Published March 1, 2006 | public
Journal Article Open

Analysis and equalization of data-dependent jitter

Abstract

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s.

Additional Information

© Copyright 2006 IEEE. Reprinted with permission Manuscript received June 30, 2005; revised October 24, 2005. [2006-02-27] This work was supported by the National Science Foundation and an IBM Ph.D. Fellowship. The authors would like to thank B. Analui at Caltech for helpful discussions. They also appreciate the support of IBM Research at Yorktown Heights, NY, for providing foundry access. Additionally, the authors thank the Rogers Corporation for the generous donation of duroid.

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August 22, 2023
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