Published February 1, 2005
| public
Book Section - Chapter
Open
A 10Gb/s eye-opening monitor in 0.13μm CMOS
Abstract
An eye-opening monitor circuit in 0.13 μm CMOS operates from 1 to 12.5Gbit/s at 1.2V supply. It maps the input eye to a 2D error diagram with 68dB mask error dynamic range. Left and right halt of the eye are monitored separately to capture asymmetric eyes. Tested input amplitude is from 50 to 400mV. The chip consumes 330mW and works at 10Gb/s with a supply voltage as low as 1V.
Additional Information
© Copyright 2005 IEEE. Reprinted with permission. Publication Date: 6-10 Feb. 2005. The authors thank J. Tierno, T. Zwick, M. Beakes, S. Gowda, F. Friedman, M. Soyuer, M. Oprysko of IBM and J. Ewen of JDSU for technical feedback and support.Files
ANAisscc05.pdf
Files
(839.3 kB)
| Name | Size | Download all |
|---|---|---|
|
md5:063f867a999ad9cd1b741b288fe27ffc
|
839.3 kB | Preview Download |
Additional details
- Eprint ID
- 10906
- Resolver ID
- CaltechAUTHORS:ANAisscc05
- Created
-
2008-06-19Created from EPrint's datestamp field
- Updated
-
2021-11-08Created from EPrint's last_modified field