An efficient asynchronous multiplier

Abstract

An efficient asynchronous serial-parallel multiplier architecture is presented. If offers significant advantages over conventional clocked versions, without some of the drawbacks normally associated with similar asynchronous techniques, such as excessive area. It is shown how a general asynchronous communication element can be designed and illustrated with the CMOS multiplier chip implementation. It is also shown how the multiplier could form the basis for a faster and more robust implementation of the Rivest-Sharmir-Adleman (RSA) public-key cryptosystem.

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