A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection
Abstract
A 41.2 nJ/class, 32-channel, patient-specific onchip classification architecture for epileptic seizure detection is presented. The proposed system-on-chip (SoC) breaks the strict energy-area-delay trade-off by employing area and memoryefficient techniques. An ensemble of eight gradient-boosted decision trees, each with a fully programmable Feature Extraction Engine (FEE) and FIR filters are continuously processing the input channels. In a closed-loop architecture, the FEE reuses a single filter structure to execute the top-down flow of the decision tree. FIR filter coefficients are multiplexed from a shared memory. The 540 × 1850 μm 2 prototype with a 1kB register-type memory is fabricated in a TSMC 65nm CMOS process. The proposed on-chip classifier is verified on 2253 hours of intracranial EEG (iEEG) data from 20 patients including 361 seizures, and achieves specificity of 88.1% and sensitivity of 83.7%. Compared to the state-of-the-art, the proposed classifier achieves 27 × improvement in Energy-AreaLatency product.
Additional Information
© 2018 IEEE.Additional details
- Eprint ID
- 90620
- DOI
- 10.1109/EMBC.2018.8513243
- Resolver ID
- CaltechAUTHORS:20181102-143405625
- Created
-
2018-11-02Created from EPrint's datestamp field
- Updated
-
2023-03-15Created from EPrint's last_modified field