Published July 1985
| Published
Journal Article
Open
A Hardware Architecture for Switch-Level Simulation
- Creators
- Dally, William J.
- Bryant, Randal E.
Abstract
The Mossim Simulation Engine (MSE) is a hardware accelerator for performing switch-level simulation of MOS VLSI circuits [1], [2]. Functional partitioning of the MOSSIM algorithm and specialized circuitry are used by the MSE to achieve a performance improvement of /spl gt/ 300 over a VAX 11/780 executing the MOSSIM II program. Several MSE processors can be connected in parallel to achieve additional speedup. A virtual processor mechanism allows the MSE to simulate large circuits with the size of the circuit limited only by the amount of backing store available to hold the circuit description.
Additional Information
© 1985 IEEE. Manuscript received January 20, 1985; revised March 28, 1985. This research was supported by the Defense Advanced Research Projects Agency, ARPA order number 3771, and monitored by the Office of Naval Research under Contract N00014-79-C-0597.Attached Files
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Additional details
- Eprint ID
- 79368
- Resolver ID
- CaltechAUTHORS:20170725-174955797
- 3771
- Defense Advanced Research Project Agency (DARPA)
- N00014-79-C-0597
- Office of Naval Research (ONR)
- Created
-
2017-07-26Created from EPrint's datestamp field
- Updated
-
2021-11-15Created from EPrint's last_modified field