Problems and approaches for a Teraflop processor

Abstract

This paper discusses problems associated with designing a processor capable of sustaining a teraflop (10^12 floating point operations per second) of processing power. Several researcher have speculated on achieving this performance. The technical problems of a practical design are shown to be formidable. However, none of these problems requires a technology breakthrough for their solution. The predictable advances of the next generation of technology together with a major engineering effort is all that will be required to build such a parallel machine with usable teraflop processing power.

Additional details