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Published July 2016 | public
Journal Article

A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS

Abstract

This paper describes an ultralow-power VCSEL transmitter in 32 nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. Driving the VCSEL in this condition increases its inherent nonlinearity. Conventional pre-emphasis techniques cannot compensate for this effect because they have a linear response. To overcome this limitation, a nonlinear equalization scheme is proposed. A dynamic VCSEL modelling technique is used to generate the time-domain optical responses for "one" and "zero" bits. Based on the asymmetry of the two responses, the rising and falling edges are equalized separately. Additionally, instead of using fixed bit delays, the equalization delay is selected based on the bias current of the VCSEL. The efficiency of the proposed modelling and equalization technique is evaluated through simulations and measurements. The transmitter achieves energy efficiency of 0.77 pJ/b at 20 Gb/s and occupies 100 µm x 60 µm active silicon area.

Additional Information

© 2016 IEEE. Manuscript received January 08, 2016; revised March 17, 2016; accepted March 31, 2016. Date of publication May 5, 2016; date of current version July 25, 2016. This paper was approved by Guest Editor Patrick Chiang. The authors would like to thank D. K. Serkland and Sandia National Laboratories for providing the VCSELs and helping with the optical measurement setup, and DARPA LEAP for chip fabrication.

Additional details

Created:
August 20, 2023
Modified:
October 20, 2023