Welcome to the new version of CaltechAUTHORS. Login is currently restricted to library staff. If you notice any issues, please email coda@library.caltech.edu
Published 1999 | Published
Book Section - Chapter Open

Scaling of MOS Technology to Submicrometer Feature Sizes

Abstract

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.

Additional Information

© 1999 Perseus Books. Reproduced from Journal of VLSI Signal Processing, 8, 9-25 (1994) Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Attached Files

Published - 388894.pdf

Files

388894.pdf
Files (4.5 MB)
Name Size Download all
md5:a83f1b17c5eec5ff7729f7ee0d6f8123
4.5 MB Preview Download

Additional details

Created:
August 19, 2023
Modified:
March 5, 2024