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Published November 2013 | public
Journal Article

Reconfigurable Processor for Energy-Efficient Computational Photography

Abstract

This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors.

Additional Information

© 2013 IEEE. Manuscript received June 03, 2013; accepted August 06, 2013. Date of publication October 07, 2013; date of current version October 19, 2013. This paper was approved by Associate Editor Stefan Rusu. This work was supported by the Foxconn Technology Group. The authors would like to thank the TSMC University Shuttle Program for chip fabrication and Prof. F. Durand and J. Regan-Kelley for valuable feedback and suggestions.

Additional details

Created:
August 19, 2023
Modified:
October 20, 2023