A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication
Abstract
This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-μA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm^2 silicon area.
Additional Information
© 2012 IEEE. Manuscript received June 20, 2012; revised August 28, 2012; accepted October 24, 2012. Date of publication December 20, 2012; date of current version January 24, 2013. This paper was approved by Associate Editor Anthony Chan Carusone.Additional details
- Eprint ID
- 37707
- DOI
- 10.1109/JSSC.2012.2227612
- Resolver ID
- CaltechAUTHORS:20130401-143245883
- Created
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2013-04-04Created from EPrint's datestamp field
- Updated
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2023-03-15Created from EPrint's last_modified field
- Other Numbering System Name
- INSPEC Accession Number
- Other Numbering System Identifier
- 13251810